Decimal Floating Point for future processors


Fahmy, H.A.H.; ElDeeb, T.; Hassan, M.Y.; Farouk, Y.; Eissa, R.R.;
Electron. & Commun. Dept., Cairo Univ., Cairo, Egypt


Many new designs for Decimal Floating Point (DFP) hardware units have been proposed in the last few years. To date, only the IBM POWER6 and POWER7 processors include internal units for decimal floating point processing. We have designed and tested several DFP units including an adder, multiplier, divider, square root, and fused-multiply-add compliant with the IEEE 754-2008 standard. This paper presents the results of using our units as part of a vector co-processor and the anticipated gains once the units are moved on chip with the main processor.

This paper appears in: Microelectronics (ICM), 2010
International Conference on
Issue Date: 19-22 Dec. 2010
On page(s): 443 - 446
Location: Cairo
Print ISBN: 978-1-61284-149-6
INSPEC Accession Number: 11763807
Digital Object Identifier: 10.1109/ICM.2010.5696183
Date of Current Version: 20 January 2011