Algorithm and architecture for on-line decimal powering computation


Hassan, M.Y.  ElDeeb, T.  Fahmy, H.A.H. 
SilMinds, Maadi, Helwan, Egypt


An architecture for the computation of a decimal powering function is presented in this paper. The algorithm consists of a sequence of overlapped operations: 1) digit recurrence logarithm, 2) sequential multiplication, and 3) on-line antilogarithm. A correction scheme is introduced between the overlapped operations to guarantee correct on-line calculations. Execution times are estimated for decimal64 and decimal128 formats of the IEEE 754-2008 standard for floating point arithmetic.

This paper appears in: Signals, Systems and Computers (ASILOMAR), 2010 Conference Record of
the Forty Fourth Asilomar Conference on
Issue Date: 7-10 Nov. 2010
On page(s): 1158 - 1162
Location: Pacific Grove, CA
ISSN: 1058-6393
Print ISBN: 978-1-4244-9722-5
INSPEC Accession Number: 11972617
Digital Object Identifier: 10.1109/ACSSC.2010.5757586
Date of Current Version: 29 April 2011