Authors
Samy, Rodina; Fahmy, Hossam A. H.; Raafat, Ramy; Mohamed, Amira; ElDeeb, Tarek; Farouk, Yasmin;
SilMinds, LLC. Maadi, 11431, Helwan, Egypt
Abstract
This paper presents the first hardware implementation of a fully parallel decimal floating-point fused-multiply-add unit performing the operation ± (A × B) ± C on decimal floating-point operands. The proposed design is fully compliant with the IEEE 754–2008 standard and supports the two standard formats decimal64 and decimal128. Furthermore, the proposed design may be controlled to perform the multiplication or the addition/subtraction as standalone operations. Our decimal floating-point FMA may be pipelined so that a complete resultant decimal floating-point is available each clock cycle.
This paper appears in: Circuits and Systems (MWSCAS), 2010
53rd IEEE International Midwest Symposium on
Issue Date: 1-4 Aug. 2010
On page(s): 529 - 532
Location: Seattle, WA, USA
ISSN: 1548-3746
Print ISBN: 978-1-4244-7771-5
Digital Object Identifier: 10.1109/MWSCAS.2010.5548746
Date of Current Version: 16 August 2010