Energy and Delay Improvement via Decimal Floating Point Units


Fahmy, H.;   Raafat, R.;   Abdel-Majeed, A.M.;   Samy, R.;   ElDeeb, T.;   Farouk, Y.;  
Electron. & Commun. Dept., Cairo Univ., Cairo, Egypt 


Interest in decimal arithmetic increased considerably in recent years. This paper presents new designs for decimal floating point (DFP) addition, multiplication, fused multiply-add, division, and square root. It stresses the importance of energy savings achieved by hardware implementations of the IEEE standard for decimal floating point. To the best of the authors knowledge, this is the first work to discuss energy savings in DFP and the first to present a hardware implementation of a fused multiply-add. Our Newton-Raphson based divider is over three times faster than the similar design previously reported.

This paper appears in: Computer Arithmetic, 2009. ARITH 2009.
19th IEEE Symposium on
Issue Date: 8-10 June 2009
On page(s): 221 - 224
Location: Portland, OR
ISSN: 1063-6889
Print ISBN: 978-0-7695-3670-5
INSPEC Accession Number: 10844937
Digital Object Identifier: 10.1109/ARITH.2009.21 
Date of Current Version: 25 August 2009

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