|
An average computer user speeds up the applications by over twenty times and
slashes the energy use to less than 5% if decimal hardware units are employed.
Interest in decimal arithmetic increased considerably in
recent years. This IP family presents new designs for decimal
floating point (DFP) addition, multiplication, fused multiply-add,
division, and square root. It stresses the importance
of energy savings achieved by hardware implementations
of the IEEE 754-2008 standard for decimal floating point.
SilMinds is the first company worldwide to
discuss energy savings in DFP and the first to present
a hardware implementation of a fused multiply-add. Our
Newton-Raphson based divider is over three times faster
than the similar design previously reported.
A small presentation for the decimal technology may be downloaded from here |
|
Read more…
|
|
|
SilMinds is developing different versions of DecSqrt64 core. The available version in market now is the low cost version which is Newton-Raphson DecSqrt64 (NRDecSqrt64). The high performance version of DecSqrt64 is based on SRT algorithm. It will be released by October 2008. NRDecSqrt64 is a Decimal Floating point Square root. It computes the square root of an operand. NRDecSqrt64 is fully compliant with IEEE 754r Standard. NRDecSqrt64 input is encoded in the Decimal Interchange Format Encoding. NRDecSqrt64 is based on the multiplicative algorithm using Newton-Raphson iterative method to compute the final result. It takes 4 iterations to compute the final result. For more information, please download NRDecSqrt64 datasheet. |
|
|
SilMinds is developing different versions of DecDiv64 core. The available version in market now is the low cost version which is Newton-Raphson DecDiv64 (NRDecDiv64). The high performance version of DecDiv64 is based on SRT algorithm. It will be released by October 2008. NRDecDiv64 is a Decimal Floating point Division. It computes the Quotient of two operands. NRDecDiv64 is fully compliant with IEEE 754r Standard. NRDecDiv64 inputs are encoded in the Decimal Interchange Format Encoding. NRDecDiv64 is based on the multiplicative algorithm using Newton-Raphson iterative method to compute the final quotient. It takes 4 iterations to compute the final quotient. For more information, please download NRDecDiv64 datasheet. |
|
|
DecFMA64 is the first Decimal Floating point Fused Multiply Add IP Core available in the market. It computes the Multiply-Add Operations ± (A×B) ±C of three inputs. DecFMA64 is fully compliant with IEEE 754r Standard. DecFMA64 inputs are encoded in the Decimal Interchange Format Encoding. The available version of DecFMA64 is the low cost version. SilMinds will release the high performance version of DecFMA64 by September 2008. For more information, please download DecFMA64 datasheet. |
|
|
DecMult128 is a novel Parallel Decimal Floating Point Multiplier. It computes the Product of two operands. DecMult128 is fully compliant with IEEE 754r Standard. DecMult128 inputs are encoded in the Decimal Interchange Format Encoding. DecMult128 is provided in two versions: HSDecMult128 and LCDecMult128. For more information, please download DecMult128 datasheet. |
|
|
|
