Sayed-Ahmed, A.A.R. Fahmy, H.A.H. Hassan, M.Y.
Electron. & Commun. Dept., Cairo Univ., Giza, Egypt
Decimal floating-point designs require a verification process to prove that the design is in compliance with the IEEE Standard for Floating-Point Arithmetic (IEEE Std 754-2008). Our work represents three engines, the first engine for the verification of decimal addition-subtraction operation, the second for the verification of decimal multiplication operation, and the third for the verification of decimal fused-multiple-add operation. Each engine solves constraints describing all corner cases of the operation, and generates test vectors to verify these corner cases in the tested design. The paper describes the constraints of each operation and the steps of each engine to solve these constraints.
This paper appears in: Signals, Systems and Computers (ASILOMAR), 2010 Conference Record of
the Forty Fourth Asilomar Conference on
Issue Date: 7-10 Nov. 2010
On page(s): 1153 - 1157
Location: Pacific Grove, CA
Print ISBN: 978-1-4244-9722-5
INSPEC Accession Number: 11972616
Digital Object Identifier: 10.1109/ACSSC.2010.5757585
Date of Current Version: 29 April 2011