A decimal fully parallel and pipelined floating point multiplier


Raafat, R.  Abdel-Majeed, A.M.  Samy, R.  ElDeeb, T.  Farouk, Y.  Elkhouly, M.  Fahmy, H.A.H. 
SilMinds, LLC, Giza


Decimal arithmetic is important in several commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents a fully parallel Decimal64 floating point (FP) multiplier compliant to IEEE Std 754-2008 for floating point arithmetic. The proposed multiplier possesses novel methods to target low latency. The proposed design is based on a previously published fixed point multiplier that uses a novel BCD-4221 recoding for decimal digits to improve the area and latency of the partial product generation and the partial product reduction tree. Several enhancements are introduced to the design; the final carry propagation adder is implemented using a fully parallel decimal adder with a Kogge-Stone prefix tree, the sticky bit is generated in parallel to the shifter to reduce the critical path delay. The design is extendable to support Decimal128 floating point multiplication. The multiplier is hardware verified for functionality on an FPGA.

This paper appears in: Signals, Systems and Computers, 2008
42nd Asilomar Conference on
Issue Date: 26-29 Oct. 2008
On page(s): 1800 - 1804
Location: Pacific Grove, CA
ISSN: 1058-6393
Print ISBN: 978-1-4244-2940-0
INSPEC Accession Number: 10718827
Digital Object Identifier: 10.1109/ACSSC.2008.5074737
Date of Current Version: 12 June 2009

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