SilMinds

DecAdd64/128

DecAdd64 and DecAdd128 IP core units are novel DFP Adder designs, offered in 64-bit and 128-bit versions. The Adder unit computes the Sum or the Difference of two vector Operands. Inputs are encoded in Decimal Interchange Format. The product is fully compliant with the IEEE 754-2008 Standard.

Download DecAdd64/128 Data Sheet

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